Silicon-on-insulator ("SOI") field effect transistors ("FET's"), particularly wide SOI FET's in pass gate applications, suffer a parasitic bipolar currents the effects of which are most severe when the circuit is initially turned on after being idle for a long period of time, i.e. a time in the range of milliseconds. This is because the floating body of the SOI FET can develop a body charge over time. The amount of such body charge will depend on the potentials at the source, drain, and gate terminal electrodes of the SOI FET. The maximum amount of charging occurs when the gate is completely turned off and both the source and drain electrode are biased at the highest potential vdd. During the subsequent switching of the source or drain electrode of the SOI FET, the accumulated body charge will be discharged by means of a transient bipolar current. This parasitic current degrades performance, including noise and timing performance. See, for example, C. Chuang, P.Lu, and C. Anderson, SOI for Digital CMOS VLSI: Design Considerations and Advances, Proceedinigs of the IEEE, v. 86, No. 4, April 1998, p. 689-720, which is hereby incorporated by reference (discussing the nature of and occasion for the parasitic current in connection with the description therein of FIGS. 1 and 2), and C. I-Isieh et al., Methods to Enhance SOI SRAM Cell Stability, U.S. Pat. No. 5,774,411, which is hereby incorporated by reference (discussing, in the Background of the Invention section, the parasitic, lateral, bipolar transistor formed by the source, drain and channel, i.e., floating body, region of an FET). Pass gates are particularly susceptible to parasitic bipolar current because it is not uncommon in pass gate applications for both the source and drain of a pass gate to be driven to a relatively high voltage level, and because it is not uncommon for pass gates to be relatively wide.
A number of circuit structures are known for mitigating this problem in a variety of contexts. For example, for a number of applications, including pass gates, it is known to connect the SOI NFET body to the NFET gate. Id. at p. 706. This has the beneficial effect of minimizing Vt loss (aka "dynamic Vt control"), improving drive, and suppressing leakage, but is disadvantageous from the standpoint of area increase and incompatibility with bulk design.
It is also known to actively bias the body of SOI NFET and PFET devices in an inverting output stage of a driver. Id. at 709 (showing a network of FET's responsive to the input to and output from the SOI output stage). Such an arrangement also has the beneficial effect of minimizing Vt loss, improving drive. and suppressing leakage, but has disadvantages of more expensive fabrication process, significantly larger area for the extra diode and capacitor, and increasing input capacitance (which slows down the circuit). It is also known to discharge the body of a SOI FET responsive to a signal timed to occur shortly before the gate of the FET is selected (hereinafter, a "pre-discharge signal"), or responsive to the accumulated charge on the body. This discharging has the possible benefit of reducing parasitic bipolar current during functional, initial cycle switching, provided that the discharging is early enough or that the discharge device is large enough with respect to the charge on the body to sufficiently discharge the body during the discharging interval before the gate is selected. In addition to these limitations, it also disadvantageously requires that a timing signal be generated for the pre-discharge signal.
Therefore, although there are known circuits and techniques for mitigating parasitic, bipolar current in an insulated body FET, because of the disadvantages described above, and others, a need remains for improved methods and structures for mitigating such parasitic, bipolar current.